The Carbon Nanotubes (CNT) are viewed to be a new key element for future electronics and photonics. In the CNT, such unique properties as quantization of the electron spectrum, ballistic electron propagation along the tube, current densities as high as 109 A/cm2, existence of the semiconductor phase, possibilities for n- and p-doping with a high carrier mobilities, as well as excellent thermal conductance, make the nanotubes a great candidate for future novel high-speed, high efficiency electronic and photonic devices.
It is extremely important that all these outstanding properties are related to the semiconductor single walled carbon nanotubes (SWCNT), which are expected to be the building blocks for multiple semiconductor devices and circuits, with the properties far superior than those in the traditional semiconductor counterparts.
The proof-of-concept design, wherein a single nanotube is placed on the substrate between the contacts, is utilized in essentially all publication on this topic, for both CMOS circuit (see e.g. V. Derycke et al. Nano Letters 1, p. 453, 2001) and individual transistors (see also E. Ungersboeck, et al, IEEE Transactions on nanotechnology, V4, p. 533, 2005). The drawback of this method is its impracticality for any scale of circuit integration: placement of multiple identical nanotubes to enhance the output current or to form new circuit elements requires a special micro-manipulator and thus precludes any possibility of IC mass manufacturing. The future success of CNT devices will rely on emergence of a cost efficient manufacturing process that will ensure a high-yield and cost efficiency above the modern FET and CMOS technologies.
The present invention is related to this technology. It is based on the growth of a lithographically controlled nanotube array on a metal electrode normally to the electrode plane, followed by sequential deposition of dielectric and metal layers to produce a solid platform for attachment of a second contact to the nanotube tips, thereby forming source and drain electrodes. The transistor gate electrode is made as a third conductive layer sandwiched between the dielectric layers and placed somewhere in the middle of the nanotube length.
Such a technology was described in the U.S. Pat. No. 7,851,784 filed by A. Kastalsky, where several nanotube array devices and methods for their fabrication have been disclosed. Shown in FIG. 1 as a Prior Art, is the drawing from this patent wherein the CNT FET consists of the nanotube 57 grown normally to the substrate, and the gate electrode 51 is attached to the sidewall of every nanotube 57 in the array through a layer of insulator 54. The key element is the metal layer 51 in the middle of the nanotube length, sandwiched between two insulator layers 52 and 53. During deposition of the first insulator layer 52, a thin layer of insulation material will also be deposited on the nanotube walls, thereby forming a gate insulator layer 54 around each nanotube. It is then followed by deposition of the gate metal layer 51 and the insulator layer 53. After polishing of the insulator layer 53 and exposure of the nanotube tips, the top metal layer 55 (the drain electrode) is deposited to complete the structure. Such a design of the CNT transistor, with the nanotube buried within sequentially deposited insulating and metal layers, allows realization of the planar technology for commercial manufacturing of the CNT-based devices and integration circuits.
The above described device technology requires vertical growth of the semiconductor type SWCNT. Typically, they are 1-3 nm in diameter, and are CVD grown from tiny spheres of the catalytic metals, such as Ni, Fe, Cd, formed after melting the nano-pads deposited on the original contact electrode. The nano-pads are designed to be a few nm in diameter to produce a SWCNT. This is a rather challenging job since the current best resolution e-beam lithography can produce pads of only ˜20 nm in diameter. For the smallest reliable thickness of the catalytic layer of 0.5 nm, this results in a sphere diameter of ˜6-7 nm, which is too large for making SWCNT. There is therefore a necessity to reduce the metal pad diameter below the modern e-beam capabilities. One of such possibilities was disclosed in the US Patent Application #2011/0186808 where a 20 nm opening made by e-beam lithography was designed to be further reduced down to a few nm in diameter using the photo-resist melting procedure. At temperatures elevated above 90 C, the photo-resist is known to soften and behave like a viscous fluid moving toward the opening center thereby shrinking the aperture. After deposition of a ˜0.5 nm-thick catalytic metal layer and then metal lift-off, the metal pads with the diameter defined by the reduced aperture will be formed. The resultant effect of shrinking the opening depends on several factors, such as temperature, photoresist thickness and its properties, and duration of the procedure. All these factors must be kept under strict control to obtain the desirable type of the nanotubes with uniform properties over the nanotube array.
The disclosed according to the present invention technique also relates to forming nano-pads of the catalytic metal. Unlike the above discussed method, relying on the photo-resist softening, the present invention is based on a “shadow mask” for the catalytic metal deposition, when the metal evaporation source is positioned under the angle relative to the plane of the openings, while the photo-resist height around the aperture serves as a shadow mask.
Two different shadow mask processes are disclosed, according to the present invention. In one case, the photo-resist itself, having the thickness close to the opening diameter, is utilized as the shadow mask. In the second case, prior to forming the opening, a 20-30 nm—thin layer of insulator is deposited on the original metal contact. The 20 nm opening in the photo-resist is then made using the e-beam lithography, and the insulator is etched within the aperture to expose the bottom contact metal layer. Then photo-resist is removed and the remaining insulator layer around the hole serves as the shadow mask. In both cases, the original opening is made on the metal contact in the shape of a 20×20 nm2 square, and the resultant shadow mask deposition process creates a small metal square pad in one of the corners of the original opening.
The disclosure and analysis of these two shadow mask techniques for obtaining nano-pads of catalytic material are the main objects of the present invention.